cyrix 6x86 การใช้

• Later in 1995, Cyrix released its best-known chip, the Cyrix 6x86 ( M1 ).
• Some processors ( eg . the Cyrix 6x86-P200 + ) require a 75-megahertz ( MHz ) bus.
• The Pentium; it also simplified speculative execution and allowed higher clock frequencies compared to designs such as the advanced Cyrix 6x86.
• Modern x86 design acquired these techniques around 1995 with the releases of Pentium Pro, Cyrix 6x86, Nx586, and AMD K5.
• It was also available in a PC compatible system with a 166 MHz DOS card containing 16 MB of RAM and a Cyrix 6x86 processor.
• Similar to the AMD K5, the Cyrix 6x86 was a design far more focused on integer per-clock performance than clock scalability, something that proved to be a strategic mistake.
• The "'Cyrix 6x86 "'( codename M1 ) is a sixth-generation, 32-bit x86-compatible microprocessor designed by Cyrix and manufactured by IBM and SGS-Thomson.
• Whether this processor belongs in the fourth or fifth generation of x86 processors can be considered a matter of debate as the processor was based on the 5x86 ( a scaled down version of the Cyrix 6x86 ).
• The Cyrix 6x86-P200 came with 32 megabytes of extended data out, or EDO, random-access memory, and 256 kilobytes of pipelined burst cache, a method of speeding how data moves into the main processor.
• With the Cyrix 6x86 and AMD's forthcoming 5K86 ( K5 ) and 6K86 ( K6 ), this is easy : Since these processors are pin-compatible with Intel's Pentium, an identical motherboard and peripherals can be used.
• The Cyrix 5x86 processor, codename " M1sc ", was based on a scaled-down version of the " M1 " core used in the Cyrix 6x86, which provided 80 % of the performance for a 50 % decrease in transistors over the 6x86 design.
• It had the 32-bit memory bus of an ordinary 486 processor, but internally had much more in common with fifth-generation processors such as the Cyrix 6x86, the AMD K5, and the Intel Pentium, and even the sixth-generation Intel Pentium Pro.
• Other changes to the core include a 6-stage pipeline ( vs . 5 on P5 ) with a return stack ( first done on Cyrix 6x86 ) and better parallelism, an improved instruction decoder, 32 KB L1 cache with 4-way associativity ( vs . 16 KB with 2-way on P5 ), 4 write buffers ( vs . 2 on P5 ) and an improved branch predictor taken from the Pentium Pro, with a 512 entry buffer ( vs . 256 on P5 ).